The present invention generally relates to a circuit for generating and recognizing a serial ID code of a device, and in particular to a processor-based circuit capable to recognize a device code with a simplified circuit structure.
Processor-based electronic devices and peripheral devices associated therewith are usually provided with a device code to be read and recognized by processors thereof for identification purposes in order to establish proper data connection therebetween. FIG. 8 of the attached drawings shows an example of a conventional device code recognizing circuit which makes use of a number of jumpers (J) and diodes (D) serially connected between an I/O terminal (A1) and a key array (X) of a microprocessor (A). In the example shown in FIG. 8, eight sets of jumpers (J) and diodes (D) are used and respectively connected to eight input terminals (I0-I7) of the key array (X). The I/O terminal (A1) sequentially sends out high and low signals for being read by the input terminals (I0-I7) and thus there are 28=256 possible combinations of code. However, since the I/O terminal (A1) is connected to the input terminals (I0-I7), there must be diodes (D) therebetween in order to avoid undesired currents therethrough and prevent interference with the regular input function of the input terminals (I0-I7) serving as part of the key array (X). The more input terminals (I0-I7) used, the more diodes (D) are needed. This increases not only costs but also complexity of the circuit.
FIG. 9 shows another example of the conventional device code recognizing circuited wherein four I/O terminals (ID0-ID3) of a microprocessor (Axe2x80x2) are respectively connected with switches (SW). The switches (SW) allows user""s setting of the device code. No connection between the I/O terminals (ID0-ID3) and the input terminals (R0-R7) is needed thereby eliminating the current problem encountered in the example of FIG. 8 and simplifying the structure of the circuit. However, the number of combinations of code is limited to only 24=16. To increase the number of possible code combination, additional terminals of the microprocessor (Axe2x80x2) must be used and this imposes additional limitation to the utilization of the microprocessor (Axe2x80x2).
Thus, it is desired to have a device code recognizing circuit which overcomes the problems encountered in the prior art.
Accordingly, an object of the present invention is to provide a device code recognizing circuit having a simple structure but providing the largest number of possible code combinations.
Another object of the present invention is to provide a device code recognizing circuit capable to provide the largest number of possible code combinations with the least number of terminals of a microprocessor.
A further object of the present invention is to provide a device code recognizing circuit wherein generation of a device code associated therewith does not interfere with the regular operation of the device.
To achieve the above objects, in accordance with the present invention, there is provided a device code recognizing circuit comprising a microprocessor forming an array having input pins and output pins and a code generation circuit connected to the microprocessor. The code generation circuit includes signal input terminals connected to input pins of the array and signal output terminals connected to I/O terminals of the microprocessor. The signal output terminals are sequentially and selectively set to one of low level condition and high impedance condition. The input pins of the microprocessor to which the signal input terminals of the code generation circuit are connected serially read signals from the code generation circuit for provision the signals to the microprocessor to form a device code associated therewith.